This invention relates generally to digital logic circuitry, and, in particular, to a divide circuit for dividing an input signal of given frequency by a non-integer quantity.
In the field of television displays, video games, home computing systems and related arts, it is often necessary to generate a clock frequency which is a submultiple of a commonly availble television internal clock frequency of approximately 3.5 megahertz. The present invention has utility, for example, in the video display or video game environment in which a television display means is used in conjunction with a microcomputer and such additional circuits as a video display generator, video encoder, and the like, which have internal operating frequencies of approximately one megahertz. The present invention also has utility in other types of digital circuits employed in the processing of data in binary form, as will be apparent to one skilled in the art.
A known prior art divide circuit suitable for dividing a clock of 3.5 megahertz by the quantity 3.5 utilizes a 7 megahertz clock, representing half cycles of the 3.5 megahertz clock. Such circuit is expensive to manufacture since all of its components must be capable of 7 megahertz operation. Moreover, such circuit is susceptible to noise spikes which may be misinterpreted as the 7 megahertz clock pulses. There is thus a need for a relatively inexpensive divide circuit for dividing an input signal of given frequency by a non-integer divisor, which circuit utilizes an internal clock of frequency no greater than that of such imput signal.